instantly available pci card power management 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 9/99 1 introduction today, pcs need to remain constantly connected to the outside world, but at the same time consume minimum power. even when looking ?idle?, it is still possible to receive a message from the internet or an incoming fax or phone call. the pc must automatically go from ?sleep? mode to ?on? mode; in other words, an ?instantly available? pc (iapc). the challenge is to maintain a system?s modem or local area network (lan) connectivity on a desktop pc/workstation while at the same time minimizing power consumption. these power management features are called wake-on-ring (or wake- on-modem), wake-on-lan, and wake-on-pme (power management event). the main qualities/benefits of such a system are: ? listening: available anytime to receive messages from the outside world, and ? reacting: responding anytime to do a specific operation (maintenance?), and ? saving energy and being silent in the idle mode. the ? onnow ? initiative by microsoft defined the new requirements for the system that affect both software and hardware aspects of the pc: windows operating system, applications, device drivers, and hardware within the system. all these elements must work together in order to provide a fully transparent power management system. this note will focus only on the hardware aspects. acpi system design an instantly available pc appears to be ?off?, yet it can snap back to its full ready state within seconds and respond to the phone ringing in time to service the call. in order to meet these requirements a recommendation, the advanced configuration and power interface specification (acpi), has been defined by intel , microsoft , and toshiba . instantly available motherboards include: acpi bios, acpi chip set, and pci slots that are compliant to the pci-pm specification. the intel chip set supports the power management features to define the acpi sleep states and also generates the signals to control power planes to turn the main power supplies on and off. the implementation includes multiple power sources and uses separate power planes in the system. each power source is selected depending on the required state demanded by the system, and one of the major requirements is to switch between power sources continuously, automatically, and without interruption. the ?sleep? state of an instantly available pc is called ?suspend to ram?. this is implemented by using: ? split power planes in the system design, and ? an auxiliary power source (v aux ) for dual mode power distribution. let?s focus on the pci (peripheral component interface) cards, where california micro device?s products have their primary applications. by definition, all pci add-on cards are connected to the motherboard through the pci bus. on the pci connector, several pins have been reserved in order to support the instantly available functionality. ? pme# (power management event) pin (pin #a19) is used to wake the system in response to a pci power management wake event such as the phone ringing. ? 3.3vaux pin (pin #a14) is used to deliver the auxiliary power of 3.3v to all the wake-up pci cards in the system. this power is always available to keep the card active even when the rest of the pci bus is without power. three different independent voltage sources are now available on the pci bus: 3.3v aux , 3.3v cc , and 5v cc . in a power plane partitioning system of an instantly available pc, the 3.3v aux is electrically isolated from the main pci 3.3v rail at all times. during normal operation, the 3.3v aux supply remains on all the time, while the other main supplies, 3.3v cc and 5v cc , can be switched on and off as needed. pci adapter card application pci network interface cards (nic) and modem cards are also designed with split power planes. thus, they are able to operate in sleep mode with only the vaux power supply and still be able to wake-up the system. some nics that operate in ?wake on lan? mode get a 5v standby through a cable that connects directly to a specific header on the motherboard. chip set voltage today, pci card chip sets or asics operate at a low voltage of 3.3v. that allows much lower power consumption than with the previous 5v modem chips. however ?older? pcs are still operating at 5v and do not have any 3.3v aux supply. ?new? pci cards must be compatible with these systems still in service, and therefore must regulate on board their own 3.3v supply from the 5v. this is made possible by using california micro devices? smartor ? power management products: the cmpwr100 and cmpwr150. in addition, there is a maximum current limitation of 375ma on the 3.3v aux . c0210699a all trademarks are the property of their respective holders. ?1999 california micro devices corp. all rights reserved. p/active ? is a registered trademark and smartor? is a trademark of california micro devices. california micro devices AP-211
9/99 2 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices AP-211 figure 1. cm pwr-100 block diagram power requirements on v aux in order to limit the power consumed by the system in the ?sleep? mode, each pci card must reduce its current consumption from the auxiliary power supply. the power operating conditions are displayed below. that means that each pci add-in card?s load on 3.3v aux must not exceed 375ma. when the board is in a sleep state with wake up event generation disabled, it must reduce its total slot current to less than 20ma which can be done several ways: ? internally disabling as much logic as possible on the board, or ? electrically isolating the 3.3 v aux pin from the auxiliary power plane of the board. dual power supply a dual mode power supply is able to deliver the same reference voltage from two separate tuned (load-wise) power sources. for example, a main power source will provide a high capacity, high efficiency 3.3v source for heavy ?runtime? loads, and a lower capacity auxiliary source, yet reasonably efficient, 3.3v source for lightly loaded ?sleeping? states. a voltage switch is required in order to select between one of these two different sources. this can be implemented with discrete schottky diodes, or more efficiently, with california micro devices? power switch, the cmpwr025. california micro devices has developed a family of smartor tm power management devices to address all these requirements whose characteristics are summarized in table 2 and will be the primary focus of this application note. table 1. power requirements for v aux table 2. summary of power management devices figure 2. cm pwr-150 block diagram in the next sections, we will discuss specific applications for the cmpwr100 and cmpwr150. in order to facilitate the design process, california micro devices has available a smartor tm evaluation board for use in the lab and to facilitate pcb layout. r e t e m a r a p n o i t p i r c s e d n i m p y t x a m t i n u v 3 . 3 x u a l a u d y b d e r e w o p 0 . 33 . 36 . 3s t l o v t i u c r i c r e w o p d e l b a n e _ x a m ip u e k a w e t a t s p e e l s5 7 3 a m d e l b a n e d e l b a s i d _ x a m i p u e k a w e t a t s p e e l s 0 2 a m d e l b a s i d gnd vout vcc1 vcc2 all these parts are general purpose smart voltage regulators and/or switches. they can be used in pci modem, pci lan card, or dual power system applications. figures 1-3 below illustrate a simplified block diagram of each of the power management devices. vout drive vcc gnd . . . v n i v t u o i t u o e g a k c a p e c i v e d n o i t c n u f ] v [ ] v [ ] a m [ 0 0 1 r w p m cd n a r o t a l u g e r 5 . 5 o t 5 . 43 . 3< 0 0 2 c i o s n i p - 8 v m o r f h c t i w s x u a r o v o t t u o v x u a 0 5 1 r w p m cr o t a l u g e r 5 . 5 o t 5 . 4 3 . 3 < 0 0 5 3 6 2 - o t n i p - 5 r oc i o s n i p - 8 v x u a 5 2 0 r w p m ch c t i w s t u p n i l a u d 5 . 5 o t 8 . 2 v 1 c c < 0 0 5 c i o s n i p - 8 r op o s m n i p - 8 v 2 c c ? electrically isolating the 3.3 v aux pin from the auxiliary power plane of the board. figure 3. cmpwr025 block diagram
9/99 3 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices AP-211 vcc output figure 5. equivalent circuit with line parasitic c + power supply r s r t l t v cc_in cm pwr-150 r l hysteresis hysteresis is illustrated in figure 4 and is defined as the difference between the enabling threshold (when the regulator turns on) and the disabling threshold (when the regulator turns off). the hysteresis level sets up the maximum level of acceptable noise or disturbance on v cc or v aux . this is particularly critical during power transitions. as shown in figure 5, the voltage seen by the device is given by: v cc_in = v cc ? (r s x i) - (r t x i) ? (l t x di/dt) assuming an ideal situation where there is no parasitic inductance, the hysteresis level should follow the equation below. v hysteresis > (r s x i) + (r t x i) where r s is the power supply output impedance and r t is the interconnect series resistance (between supply and regulator). figure 4. input voltage transient and hysteresis where, v cc is the power supply voltage, r s is the power supply output impedance, r t is the interconnect series resistance (between supply and regulator), and l t is the trace (line) inductance (between supply and regulator). in order to avoid disturbance and given the hysteresis of the devices, the recommended maximum total resistance is shown in table 3. table 3. recommended maximum series resistances during turn off to prevent chatter the worst case condition occurs during turn on, when there is in-rush current. during turn on, the current is rising from 0a to a high in-rush current. the in-rush current level and duration is increased when the initial output capacitor voltage is 0v, and when the capacitor value is larger. we can assume an in-rush current equal to twice the maximum dc load current of the device. table 4 below gives a recommendation for the maximum series resistances during turn on. table 4. recommended maximum series resistances during turn on to prevent chatter although a filter capacitor at the input can reduce the effective source impedance for short transients, long in-rush current durations may still cause chatter. cmpwr100 power management application device operation the cmpwr100 is a power management device able to generate a continuous 3.3v at 200ma from two voltage sources: a 5v main supply (v cc ) or a 3.3v auxiliary supply (v aux ). the device integrates a low dropout voltage regulator, an integrated low impedance switch, and control circuitry to switch from the v cc to v aux supply. when the 5v is present, the device automatically enables the regulator that produces 3.3v output at v out . when only the 3.3v is present, the device provides a direct connection from the v aux pin to the v out pin with a very low impedance of 0.2 w typically. this will minimize power consumption when in ?sleep? mode. the worst case is when a maximum current of 200ma is flowing which results in a power dissipation (loss) across the switch of only 8mw. s i s e r e t s y h x a m i e c n a t s i s e r e c i v e d ] v m [ ] a m [ [ w ] 0 0 1 r w p m c0 5 10 0 25 7 . 0 0 5 1 r w p m c0 5 20 0 55 . 0 5 2 0 r w p m c0 0 1 r o 0 50 0 52 . 0 r o 1 . 0 s i s e r e t s y h x a m i h s u r - n i e c n a t s i s e r e c i v e d ] v m [ ] a m [ [ w ] 0 0 1 r w p m c0 5 10 0 45 7 3 . 0 0 5 1 r w p m c0 5 20 0 0 15 2 . 0 5 2 0 r w p m c0 0 1 r o 0 50 0 0 11 . 0 r o 5 0 . 0 vcc transient time [usec] vcc [v] enable threshold disable threshold hysteresis figure 5. equivalent circuit with line parasitic v cc transient
9/99 4 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices AP-211 the cmpwr100 gives priority to the primary input v cc over the secondary input v aux . it also provides an internal reference voltage at 4.1v used to set the threshold. when the primary v cc drops below this threshold, v aux becomes the selected input source. to prevent chatter, the threshold logic has a built-in hysteresis of 150mv, and the primary source is only selected again when the v cc level exceeds 4.25v typically. all control circuitry needed to provide a smooth and automatic transition between supplies has been incorporated, allowing the v cc to be dynamically switched without loss of output voltage. a status output pin is used to indicate an acceptable v cc level. internal circuitry guarantees that high isolation is maintained between both supplies under all operating conditions. typical applications in a pci modem application, regulator is used to provide backward compatibility for 3.3v modems with ?older? systems where only 5v is provided on the pci bus. the cmpwr100 is used to generate the 3.3v on board from a 5v source. the two vaux input pins must be connected together to the 3.3vaux provided on new systems. in order to maintain regulator stability and minimize disturbance on power supplies during change over between input sources, an external 4.7 m f capacitor is required between the output and ground. the external capacitor provides the necessary filtering to minimize transients during supply change over and ensures regulator stability. most tantalum type capacitors are recommended. but the capacitor should have a low esr (equivalent series resistance). the value of the capacitor may be increased to minimize switch over transients. a bypass capacitor in the range of 1 m f to 10 m f may be connected between vcc and ground in order to filter out voltage transients. this is recommended for longer pcb trace connections between the input and the power supply, inducing large series resistance. figure 6. dual input power management circuit 2 3 7 cm pwr-100 5v main 3.3v vaux 3.3v output 1 4 vaux vaux vout1 vcc gnd status vout2 nc 6 8 5 to pci bus 4.7 m f + 0.1 m f 4.7 m f + 0.1 m f 0.1 m f as stated earlier, the status pin may be used to indicate the state of the regulator. it is active ?high? when the regulator is turned on (v cc > v thres ), and may be used to drive the gate of an external p-channel mosfet switch in parallel with the integrated pmos switch for vaux. this will provide an even lower ?on? resistance between vaux and vout, thus lowering power dissipation further. to be efficient, the external switch should have an on-resistance of less than 400m w at v gs = 3v and i d =0.2a. cmpwr150 power regulator application device operation the cmpwr150 employs a circuit topology similar to the cmpwr100 , but utilizes an external p-channel mosfet to switch vaux at current levels up to 375ma. the cmpwr150 is designed to regulate up to 500ma of continuous output current when operating from v cc . the external switch handles all the v aux requirements. the cmpwr150 exceeds the pci- defined maximum 375ma load capability. all control circuitry needed to provide a smooth and automatic transition between supplies has been incorporated. this offers trouble-free transitions between input voltages, or between sleep and wake-up modes. internal circuitry guarantees that high isolation is maintained between the v cc supply and the output under all operating conditions. the v cc to v aux isolation is achieved by disabling the external pfet when the regulator is enabled. the v out to v cc isolation is achieved by forcing the regulator pass transistor to be disabled. the v cc input is compared to a 4.1v internal threshold level. whenever v cc drops below that level, the regulator is disabled and the drive output is enabled (active low). the drive output is used to control an external p-channel mosfet switch for connecting an auxiliary 3.3v voltage source to the load. when the regulator is enabled, the drive output is set to v cc . 1. the p-channel mosfet must have a low ?on? resistance at low voltage: vaux ? (r ds(on) x i dmax ) > vout min typically, rds (on) must be less than 200m w at v gs = 3v and i d = 375ma. a typical 75mv voltage drop across the switch is applicable for most cases. 2. the mosfet must typically have a gate threshold voltage of 1v. we recommend siliconix si2301ds, fairchild fdn338p, or equivalent. 1. 2. the p-channel mosfet must have a low ?on? resistance at low voltage: v aux ? (r ds(on) x i dmax ) > v outmin typically, r ds(on) must be less than 200m w at v gs = 3v and i d = 375ma. a typical 75mv voltage drop across the switch is applicable for most cases. the mosfet must typically have a gate threshold voltage of 1v. we recommend the vishay siliconix si2301ds, fairchild fdn338p, or equivalent.
9/99 5 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices AP-211 typical applications ?cold-start? behavior a ?cold-start? situation occurs when a pc is powered on. typically, power supplies take milliseconds to reach their nominal voltage. both the 5v and 3.3v voltage sources are ramping up together. as soon as the 5v source reaches the regulator_enable 4.25v threshold, the regulator turns on. at that time the output capacitor begins to rapidly charge and pulls a large transient current which can easily exceed values of 1 ampere. it is, therefore, very important to take into consideration the parasitic series resistances and parasitic inductance between the supply voltage v cc and the device. the voltage seen by the device is given by: v ccin = v cc - (r s x i) - (r t x i) - (l t x d i / d t ) where, v cc is the power supply voltage, r s is the power supply output impedance, r t is the interconnect series resistance (between supply and the cmpwr150), and l t is the trace (line) inductance (between supply and the cmpwr150). clearly a large, rapidly changing current will create a significant change in v cc in , and if the input level drops below the regulator_disable 4.1v threshold, the regulator will turn off. the input level will then start to rise back toward 5v, turning the regulator back on. this results in an unstable state (motor boating) where the regulator turns on and off until the output capacitor is finally charged to the 3.3v level. input capacitor to minimize the unstable state effect, an input capacitor is required in close proximity to the v cc input pin. when a transition occurs from v aux to v cc , the capacitor is used as a charge reservoir to provide current to the load as well. this is especially critical when the output capacitor is not yet charged at power-up, or when the output level is much lower than figure 7. power regulator circuit 3.3v. in this case, the device will go into current limiting until vout goes back to its nominal level. a large tantalum capacitor of 10 m f or greater is recommended. output capacitor during power transitions, a previously charged capacitor will provide the current to the load until the regulator or the auxiliary supply take over. a larger tantalum capacitor at the output will improve this transition, and a value of 10 m f or greater is recommended. high frequency capacitors additionally ceramic chip capacitors can be placed next to both inputs and output pins to reduce the high frequency noise. a value of 0.1 m f is recommended. supply transient characteristics a resistive load of 6.8 w is used, setting a load current of 485ma at 3.3v. v cc power-up 0v to 5v (cold-start) with v aux open circuit ch1: v cc , offset 4.1v ch2: v out ch3: drive figure 8 shows v cc approaching the enable threshold during a 0v to 5v initial power-up transition (or cold-start). v aux is left open. when v cc reaches the 4.3v enable threshold, the regulator turns on. the large in-rush current caused by the uncharged output capacitor generates a voltage drop of about 230mv on the v cc pin. the 250mv hysteresis ensures the regulator remains enabled during the transient. figure 8 1 2 5 cm pwr-150 3.3v vaux 3.3v output 3 nc vcc drive gnd vout 4 to pci bus 5v main p-channel mosfet 10 m f + 0.1 m f 10 m f + 0.1 m f
9/99 6 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices AP-211 v cc power-down with v aux =3.3v ch1: v cc , offset 4.0v ch2: v out , offset 3.3v ch3: drive figure 10 shows v cc approaching the disable threshold during a 5v to 0v transition. v aux is set to 3.3v dc. when v cc goes down to the 4.1v disable threshold, the regulator turns off. the rebound on v cc is due to the step change of the voltage drop across the series resistance of the input. the output voltage v out experiences a negative glitch due to the parasitic resistance and inductance on the v aux line. the 250mv hysteresis ensures the regulator remains enabled during the transient. ch1: v cc , offset 4.1v ch2: v out , offset 3.3v ch3: drive ch1: v cc , offset 4.1v ch2: v out , offset 3.3v ch3: drive ch1: v cc , offset 4.1v ch2: v out , offset 3.3v ch3: drive v cc power-down with C v aux =3.6v v cc power-down with v aux =3.0v v cc power-up with v aux =3.3v ch1: v cc , offset 4.1v ch2: v out , offset 3.3v ch3: drive figure 9 shows v cc approaching the enable threshold during a 0v to 5v transition. v aux is set to 3.3v dc. in this case, the output capacitor is already set to 3.3v, so that when the regulator turns on, the in-rush current is minimized. the transition on v out is clean. the test set-up series resistance on the v cc input is estimated at about 160m w . at full load, the output voltage is above 3.2v. v cc power-up with v aux =3.0v figure 9 figure 10 figure 11 figure 12 figure 13 figures 11 - 14 show power-up and power-down transitions with v aux set to 3.0v and 3.6v.
9/99 7 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices AP-211 evaluation board the smartor tm evaluation board is intended to facilitate the use of california micro devices power management device family, and will accommodate any individual device with installation one at a time on the board. for example, operating the cmpwr100 requires populating that device and the external capacitors around it. to obtain a board, simply contact your local california micro devices sales representative or call the factory direct at 1-(800) 325-4966 and ask to be connected to applications. the board interfaces to the following signals: ? input power supply voltages v cc , v sby , v aux , and gnd. ? output voltage and signal: v out and status (or drive). it provides pad layouts for mounting two decoupling chip capacitors for each input and output of the device, as well as for a sot-23 external p-channel mosfet switch for the cmpwr150. heat spreaders are provided on the printed circuit board to improve the power dissipation for the regulator devices (i.e. cmpwr100). these are used when the devices operate under a high current load or heating condition. various sizes of heat spreaders are provided with a copper area of up to 2 inch 2 . conclusion i nstantly available pcs require unique power management devices to provide regulated voltage sources and smart switches between power sources. california micro devices provides high performance integrated solutions to reduce component count and ease the design and manufacturing cycles. california micro devices? smartor tm products allow interface card manufacturers to meet the power requirements of iapc. to find a solution to your specific requirement, call california micro devices for applications assistance. references [1] cmpwr100 data sheet, ?200ma dual input power management circuit?, rev. 9/99, california micro devices. [2] cmpwr150 data sheet, ?500ma / 3.3v smartor tm power regulator?, rev. 9/99, california micro devices. [3] cmpwr025 data sheet, ?500ma dual input smartor tm power switch?, rev. 9/99, california micro devices. [4] ?instantly available power managed desktop pc?, design guide, rev. 1.2, 9/25/98, intel corp. [5] ?instantly available pc, system power delivery requirements and recommendations?, rev. 1.0, 12/30/97, intel corp. [6] ?pci bus power management interface specification? rev. 1.1, 12/18/98, pci special interest group. v cc power-up with C v aux =3.6v ch1: v cc , offset 4.1v ch2: v out , offset 3.3v ch3: drive figure 14 ch1: v cc , offset 4.1v ch2: v out ch3: drive v cc power-up from 0v to 5v (cold-start) with v aux open bad test set-up with total series resistance of 0.7 w on v cc , by using an additional resistor of 0.5 w. figure 15 figure 15 shows a cold-start power-up transition for a test set-up with a total series resistance of 0.7 w on v cc . this is described in the ?cold-start behavior? paragraph.
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